(1) Field of the Invention
The present invention relates to a method used to fabricate a dynamic random access memory, (DRAM), device, and more specifically to a fabrication process used to selectively form components of a DRAM capacitor structure, in situ, using an ultra high vacuum, (UHV), system.
(2) Description of the Prior Art
Device performance and cost reductions are the major objectives of the semiconductor industry. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of a source/drain of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the overlying STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of a giga bit per chip, or greater, has resulted in a specific cell design in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures, and thus less storage node surface area.
The use of rough silicon, or hemispherical grain (HSG), silicon layers, as the surface layer of a DRAM capacitor, storage node electrode, where the HSG layer is comprised of convex and concave features, results in an increase in storage node surface area, when compared to counterparts fabricated with smooth silicon layers. This invention will describe a novel process in which the HSG silicon layer formation, comprised of a silicon seeding procedure, forming selectively only on exposed surfaces of an amorphous silicon storage node shape, and an anneal procedure, used to create the HSG silicon layer, from the silicon seeds, are performed in situ, in a ultra high vacuum, (UHV), system. This invention then describes the continuation of in situ procedures, performed in the UHV system, comprised of a silicon nitride layer deposition on the HSG silicon layer, followed by the oxidation of the silicon nitride layer, in another furnace, resulting in a nitride--oxide, (NO), capacitor dielectric layer, on the selectively formed HSG silicon layer. The use of the in situ processes, and UHV procedures, eliminate the formation of native oxide, that can grow on the surface of the HSG silicon layer, when using one system for the HSG silicon procedure, and a second system for the capacitor dielectric formation, thus eliminating the need for a pre-clean procedure, placed between these process steps. Prior art, such as Akram et al, in U.S. Pat. No. 5,753,558, as well as Zahurak et al, in U.S. Pat. No. 5,639,685, describe a UHV procedure, in the formation of HSG silicon layers, however these prior arts do not describe the in situ procedures for obtaining HSG silicon layers, and do not describe the nitride--oxide capacitor layers, created in situ, in a UHV system, in the present invention.